1. Field of the Invention
The present invention relates to circuits for generating clock signals, and in particular, to phase-locked loop (PLL) circuits for generating and conditioning clock signals.
2. Related Art
To generate low jitter clock signals from a noisy input clock, a conventional solution has been to use a narrow-band PLL with an external VCXO (voltage-controlled crystal oscillator) or an external VCSO (voltage-controlled surface-acoustic-wave (SAW) oscillator). This also generally results in low phase noise due to the use of a high-Q resonator, such as a crystal resonator for a VCXO, or a surface-acoustic-wave (SAW) resonator for a VCSO.
Referring to FIG. 1, conventional PLL circuits are well known in the art, and are used in many applications. A typical PLL 10 receives its input clock signal 11, which is often divided down in frequency by a divisor R with a frequency divider 12. The frequency-divided input signal 13 is compared in phase with a feedback signal 23 by a phase detector and charge pump circuit 14. This produces an error signal 15 corresponding to the difference in phase between the two input signals 13, 23. This error signal 15 is filtered by a low pass filter 16 to produce a low frequency control signal 17 for a voltage-controlled oscillator (VCO) 18. The signal 19 generated by the VCO 18 is fed back and divided down in frequency by a feedback divisor N with a frequency divider 22 to produce the feedback signal 23. The VCO output signal 19 is also often divided down in frequency by an output divisor M with an output frequency divider 20 to produce the final output signal 21.
While such a circuit 10 is well understood and reliable for use in generating signals for many uses, many modern electronic systems, such as wireless base-stations, test and measurement instruments, medical equipments, etc, require low jitter, high frequency (e.g., approaching gigahertz frequencies) clock signals from a noisy input clock or from a common stable reference clock. Low cost multiple-gigahertz LC (inductive-capacitive) VCOs are available. However, the typically poor close-in phase noise of an LC VCO limits the output clock jitter performance when PLL loop bandwidth is made narrow to filter out the input clock noise. Since high frequency VCXOs or VCSOs in the gigahertz frequency range are difficult to manufacture and are often prohibitively expensive, the conventional PLL 10 is not a good choice for generating low jitter, high frequency clock signals from noisy input clocks for low cost electronic systems.